1. Field of the Invention
The present invention relates to a hold time margin increased semiconductor device and an access time adjusting method for the same.
2. Description of the Related Art
FIG. 10 shows a schematic block diagram of part of a prior art synchronous DRAM. In the following description, a negative logic signal corresponding to a positive logic signal A will be designated as *A.
With a row address decoded signal, a word line WL is activated to select a line in a cell array 10. Data read from the line is amplified by a sense amplifier 11. For instance, according to data read from a memory cell 12, a weak voltage takes place between a pair of bit lines BL and *BL and this voltage is amplified by the sense amplifier 11. Next, with a column address decoded signal, a column selecting line CL is activated to selectively turn on a switch in a column switch circuit 13, thereby a pair of bit lines BL and *BL are connected to a pair of data bus lines DB and *DB, respectively. Voltage on the data bus lines DB and *DB are amplified by data bus amplifier 14. When a switch circuit 15 is turned on, the data is transmitted to data bus controlling circuit 16. Further, when a switch circuit 17A is turned on, the data is transmitted to an I/O data buffer circuit 18A and outputted as data DQ from an external terminal.
Since data of one line in the cell array 10 has been amplified by the sense amplifier 11, when switches in the column switch circuit 13 are successively operated, data can be successively read. The switch circuit 13, the switch circuit 15, and the switch circuit 17A are operated in synchronization with a clock to transfer data in three stage pipelines. The column switch circuit 13 and the data bus amplifier 14 compose a first stage pipe 21. The switch circuit 15 and the data bus controlling circuit 16 compose a second stage pipe 22. The switch circuit 17A and the I/O data buffer circuit 18A compose a third stage pipe 23A. The pipes 21, 22, and 23A operate in synchronization with the clock received from a clock buffer circuit 24A. The clock is generated in such a way that an external clock CLK is amplified by a clock buffer circuit 24A and then properly delayed. A clock enable signal CKE is also provided to the clock buffer circuit 24A and the clock CLK is used in a circuit not shown when the clock enable signal CKE is active.
Each of the data bus controlling circuit 16 and the I/O data buffer circuit 18A has a flip-flop circuit, and assume that they store signal states "H" and "L", respectively and therefore the signal state of the data DQ is "L". The external clock CLK is amplified by the clock buffer circuit 24A and provided as an internal clock iCLK to a control input of the switch circuit 17A through a relatively long line. After the external clock CLK becomes "H", the internal clock iCLK becomes "H" and thus, the switch circuit 17A is turned on, "H" of the output of the data bus controlling circuit 16 is stored in the flip-flop circuit of the I/O data buffer circuit 18, the drive performance is further amplified and the data DQ becomes "H". In other words, the data DQ changes in an access time ta after the external clock CLK becomes "H".
FIG. 11 shows the structure of the third pipe 23A. In this structure, as an output interface of the SDRAM, one of SSTL and LVTTL interfaces can be selected.
The lower limit of "H" and the upper limit of "L" of the SSTL interface are Vref+0.4 V and Vref-0.4 V, respectively. The lower limit of "H" and the upper limit of "L" of the LVTTL interface are 2.4 V and 0.4 V, respectively.
In FIG. 11, although the voltages of output stages (CMOSs) of the SSTL interface and the LVTTL interface are 3.3 V, the above-described upper limit and lower limit of the voltages are satisfied since the driving performance of the output stage of the SSTL interface is different from that of the LVTTL interface and a current that is provided to an input circuit (not shown) connected to the output stages of the SSTL or LVTTL interface is around 16 mA or 2 mA, respectively.
The switch circuit 17A comprises inverters 171 and 172 and transfer gates 173 and 174. The I/O data buffer circuit 18A comprises inverters 181 to 185, a NAND gate 186, a NOR gate 187, a NAND gate 188, a NOR gate 189, and transistors 18a to 18d. The transistors 18a and 18c each are pMOSFETs and the transistors 18b and 18d each are nMOSFETs. Each of the transfer gates 173 and 174 consists of a pMOS transistor and an nMOS transistor that are connected in parallel.
When the SSTL interface is active, an interface determination signal S/L is "H". In this case, the NAND gate 186 and the NOR gate 187 function as an inverter and the output stage of the SSTL interface consisting of the transistors 18a and 18b becomes active. On the other hand, the output signals of the NAND gate 188 and the NOR gate 189 are fixed to "H" and "L", respectively, thus the transistors 18c and 18d are turned off and the output stage of the LVTTL interface consisting of the transistors 18c and 18d becomes a high impedance state at its output.
When the internal clock iCLK is "L", the transfer gates 173 and 174 are off. Assume that the states of the data bus controlling circuit 16 and the I/O data buffer circuit 18A are kept "L" and "H", respectively. In this case, the signals DAT1 and DAT2 are "H", the output signal of a flip-flop circuit FF1 consisting of the inverters 181 and 182 is "H", the output signal of a flip-flop circuit FF2 consisting of the inverters 183 and 184 is "H", the transistor 18a is on, the transistor 18b is off and the data DQ is "H".
When the internal clock iCLK goes "H" from above state, the transfer gates 173 and 174 are turned on and thereby the output signals of the flip-flop circuits FF1 and FF2 transit from "H" to "L". Thus, the transistor 18a is turned off, the transistor 18b is turned on and the date DQ transits to "L". Namely, the output data DQ changes in the access time ta after the external clock CLK becomes "H".
When the interface determination signal S/L is "L", the output stage of the SSTL interface becomes a high impedance state at its output and the output stage of the LVTL interface becomes active.
Like waveforms a to d of the output signal DQ shown in FIG. 13, the access time ta varies depending on the characteristics of the SDRAM and the variation of the power supply voltage and is not constant. In an overlaid waveform of a to d, a portion XXXX represents a dead band that cannot be used. An access time tAC is a duration after the clock becomes "H" to the end of the dead band (namely, until the data is settled). A data hold time tOH is a duration after the clock becomes "H" to the beginning of the dead band. Thus, the dead band is represented by (tAC-tOH). The dead band O (tAC=tOH) represents an ideal case. With designating a cycle time of the external clock CLK as tCLK, the data established time is represented as tCLK+tOH-tAC =tCLK-(dead band). For example, if the frequency of the external clock CLK is 100 MHZ, tCLK is 10 ns. Assuming that the duration of the dead band is 3 ns, the data established time is 7 ns.
When the data DQ is read to an input circuit of another semiconductor device in synchronization with a clock CLKA that has a certain relation to the phase of the external clock CLK, a setup time tS and a hold time tH are required, and the relation of tS+tH&lt;(data established time) should be satisfied. In a normal input circuit, tS+tHO=about 3 ns. Thus, the remaining 4 ns is a margin time. However, when there are a plurality of data DQ, output timings vary among them. In addition, there are variations in signal delays on a circuit board mounting semiconductor devices. Moreover, the signal delays vary depending on the variation of the temperature and the external voltage. Thus, the margin time 4 ns is a very strict value. When the frequency of the external clock CLK is increased, the margin time becomes shorter.
Such a problem takes place with not only SDRAM, but the case that as shown in FIG. 12 a semiconductor device 31 is connected to an output of a semiconductor device 30A. An output circuit 23 and an input circuit 24 of the semiconductor device 30A correspond to the third stage pipe 23A and the clock buffer circuit 24A shown in FIG. 10, respectively.
Japanese Patent Application No. 8-339988, which assignee is the same as that of the present patent application, disclose a structure which can decrease the dead band due to the variation of the characteristics of SDRAM or the power supply voltage and so forth.
However, the present inventors have found that there were causes of a dead band that cannot be compensated by such a structure. The causes will be descried with reference to FIG. 14.
Each of FIGS. 14(A) to 14(D) shows that the data DQ is inverted in response to a rise of the external clock CKL.
FIG. 14(A) shows the case that data is outputted from the SSTL interface and is a low frequency signal.
FIG. 14(B) shows the case that data is outputted from the SSTL interface and is a high frequency signal.
FIG. 14(C) shows the case that data is outputted from the LVTTL interface and is a low frequency signal.
FIG. 14(D) shows the case that data is outputted from the LVTTL interface and is a high frequency signal.
In these cases, "high frequency" means that the frequency is so high as the dead band that cannot be compensated takes place, and "low frequency" means the reverse of that.
The access time ta in FIGS. 14(A) to 14(D) is designated as tsa, tsb, tla, and tlb, respectively. In the case of the SSTL interface and the amplitude of DQ being low, the relation of tsa=tsb is satisfied even if the data DQ is a high frequency since the data DQ can fully swing. In the case of the LVTTL interface, the relation tlb&lt;tla is obtained when the data DQ is a high frequency since the data DQ cannot fully swing. In other words, in the LVTTL interface, since the access time tlb does not accord with the access time tla, the dead band (tAC-tOH) shown in FIG. 13 increases. Even if the data is outputted from the LVTTL interface with CLK of a high frequency, when the data DQ is a low frequency, for example, the data DQ varies "L", "L", "H", "H", "L", "L", . . . with CLK, the relation tla=tlb is satisfied. Namely, when the clock CLK is a high frequency, depending on an unpredicted frequency of the data DQ, the relation tlb&lt;tla or the relation tlb=tla takes place. Thus, the margin of the hold time decreases by tla-tlb.